1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a memory cell array suitable to lower the threshold values of memory cells through the use of low power supply voltage and the microfabrication of a semiconductor memory device.
2. Description of the Related Art
Related art semiconductor memory devices include one disclosed in JP-A No. 6-176592. The patent publication discloses a configuration of a contact-type mask ROM in paragraphs 0002 to 0006 of page 2 and FIG. 2.
FIG. 11 is a block diagram showing the configuration of a semiconductor memory device which represents the mask ROM described above. The semiconductor memory device shown in FIG. 11 comprises a memory cell array 1, an address buffer 2, a row decoder 3, a column decoder 4, and a read circuit 5.
The memory cell array 1 is constituted by subarrays MS (i, j) (i=1 to m and j=1 to n) arranged in the form of a matrix. In the subarrays MS (i, j), the subarrays whose letters i's are represented by the same numeral, that is, the subarrays arranged in the same rows are connected to common block selection lines SLi (i=1 to m) and word lines WLk_i (k=1 to y and i=1 to m). Also, in the subarrays MS (i, j), the subarrays whose letters j's are represented by the same numeral, that is, the subarrays arranged in the same columns are connected to common bit lines MBLj (j=1 to n).
The address buffer 2 outputs address signals to the row decoder 3 and the column decoder 4 according to an address input.
The row decoder 3, which receives the address signal outputted from the address buffer 2 as an input, is connected to the memory cell array 1 via the block selection lines SLi (i=1 to m) and word lines WLk_i (k=1 to y and i=1 to m). The row decoder 3 makes one of the block selection lines SLi (i=1 to m) transition to a selected state and also makes one of the word lines WLk_i (k=1 to y and i=1 to m) transition to a selected state according to the inputted address signal.
The column decoder 4, which receives the address signal outputted from the address buffer 2 as an input, is connected to the bit lines MBLj (j=1 to n) and the read circuit 5. The column decoder 4 selects one from among the bit lines MBLj (j=1 to n) according to the inputted address signal to bring a path between the selected bit line MBLj (j=1 to n) and the read circuit 5 into conduction.
The read circuit 5 connected to the column decoder 4 has functions of amplifying the signal sent from the bit line MBLj (j=1 to n) selected by the column decoder 4 to output the amplified signal to the outside as data, conducting precharge or discharge, and supplying an electric charge in response to electric charge leakage.
FIG. 12 is a circuit diagram of a subarray included in the contact-type memory cell array described above of the mask ROM shown in FIG. 11. The term contact-type mask ROM means a ROM in which a state of connecting drains of memory cells to sub-bit lines is brought into correspondence with “0” of stored data and a state of not connecting them is brought into correspondence with “1” of the stored data.
The related art subarrays MS (i, j) (i=1 to m and j=1 to n) shown in FIG. 12 each comprises a N-type MOS transistor QNT and memory cells MNk (k=1 to y) each formed of a N-type MOS transistor.
In the N-type MOS transistor QNT, a gate is connected to the block selection line SL, a drain is connected to the bit line MBL, and a source is connected to a sub-bit line SBL.
In the memory cells MNk (k=1 to y), gates are connected to the word lines WLk (k=1 to y) and sources are connected to interconnections having a ground potential. When stored data is “0”, the drains of the memory cells MNk (k=1 to y) are connected to the sub-bit line SBL and when the stored data is “1”, the sub-bit line SBL is brought to the floating state.
Moreover, in the memory cell array 1 shown in FIG. 11, the block selection line SL, the word lines WLk (k=1 to y) and the bit line MBL are connected to the corresponding block selection lines SLi (i=1 to m), word lines WLk_i (k=1 to y and i=1 to m), and bit lies MBLj (j=1 to n) of the subarrays MS (i, j) (i=1 to m and j=1 to n) respectively.
The operation of reading data from, for example, the memory cell MN1 of the subarray MS (1, 1) of the semiconductor memory device having such a configuration will be described with reference to a timing chart of FIG. 13.
In response to an address input, a block selection signal SL1 is made to transition to a “H” level. Then the transistor QNT of the subarray MS (1, 1) is turned on and the bit line MBL1 and the read circuit 5 are brought into conduction by the column decoder 4. Thereafter, the bit line MBL1 and the sub-bit line SBL of the subarray MS (1, 1) are charged for a fixed time period by using the precharge function of the read circuit 5 to be made to transition to a “H” level, following which the word line WL1_1 is made to transition to the “H” level.
As a result, when the drain of the memory cell MN1 of the subarray MS (1, 1) is connected to the sub-bit line SBL, the charges supplied to the sub-bit line SBL and the line MBL1 are discharged by the memory cell MN1, thereby the sub-bit line SBL and the bit line MBL1 are pulled down to the “L” level.
When the drain of the memory cell MN1 is not connected to the sub-bit line SBL, the charges supplied to the sub-bit line SBL and the bit line MBL1 are not discharged by the memory cell MN1 and hence, the sub-bit line SBL and the bit line MBL1 keep the “H” level.
As a consequence, when the drain of the memory cell MN1 is connected to the sub-bit line SBL, the read circuit 5 outputs “L” level data to the outside. In contrast, when the drain of the memory cell MN1 is not connected to the sub-bit line SBL, the read circuit 5 outputs “H” level data to the outside.
According to such a related art, all the memory cells can be connected to the corresponding bit lines by dividing the memory cells among the subarrays instead of direct-connecting all memory cells arranged on a single bit line to a bit line. Because of this, it becomes possible to considerably reduce drops in the levels of the bit lines resulting from the fact that after precharge, the electric charges are discharged due to the occurrence of off-leakage currents from all the memory cells whose gates are connected to the nonselected word lines and whose drains are connected to the bit lines. Therefore, in microfabrication process, during which off-leakage currents increase, as well, a large-scale memory array can be realized.
Problems produced by such a related art semiconductor memory device are as described below. In the related art semiconductor memory device, the drain and source of the block selecting transistor QNT, which is the N-type MOS transistor whose gate is connected to the block selection line SL, are connected to the bit line MBLj (j=1 to n) and the sub-bit line SBL respectively instead of being grounded. Because of this, a threshold voltage is increased due to a substrate bias effect. The influence of the threshold voltage increased due to the substrate bias effect becomes great as a power supply voltage is decreased. As power consumption by portable equipment and so on including the semiconductor memory devices is reduced, power supply voltages for the semiconductor memory devices are lowered increasingly; however, the on resistance of the block selecting transistor QNT is increased considerably. On account of this, when the bit line is pre-charged by the read circuit 5, it takes time to charge the sub-bit line SBL and a charge time for the bit line BMLj (j=1 to n) lengthens. Likewise, when the electric charge supplied to the bit line MBLj (j=1 to n) is discharged as well, the discharge time lengthens due to the on resistance of the block selecting transistor QNT. Therefore, it has become impossible to rapidly read data stored in the memory device.
In addition, the threshold voltage of the block selecting transistor QNT becomes higher than that of the memory cells due to the substrate bias effect. Because of this, a power supply voltage at which the transistor QNT is turned off becomes higher than that of the memory cells, which has become a big factor that raises the power supply voltage at which the semiconductor memory device can be operated. Therefore, such a factor has become a big problem in reading data from a semiconductor memory device at a lowered voltage.
For these reasons, a method for lowering only threshold voltages at part of transistors during their manufacture and a method for reducing on resistance and substrate bias effect by boosting gate voltages at part of transistors have been proposed in recent years.
However, to lower the threshold voltages during the manufacture, a special manufacturing process is required in addition to their ordinary manufacturing process and to boost the gate voltages, there is a need to add a booster circuit having a relatively large area and hence, the areas of the semiconductor memory devices are increased. Because of these, the both methods have a drawback in that the production cost of the semiconductor memory devices rises.